In recent years, a significantly high data transfer rate is required for a data transfer between semiconductor devices (between CPUs and memories, for example). To accomplish the high data transfer rate, an amplitude of input/output signals is increasingly reduced. When the amplitude of the input/output signals is reduced, the required accuracy of an impedance to an output buffer becomes very severe.
The impedance of the output buffer varies depending on process conditions during the manufacturing. Also, during its actual use, the impedance of the output buffer is affected by a change in ambient temperature and a variation of a power source voltage. Thus, when high impedance accuracy is required for the output buffer, an output buffer having an impedance adjusting function is adopted (see Japanese Patent Application Laid-open Nos. 2002-152032, 2004-32070, 2006-203405, 2005-159702, and 2007-110615). The adjustment of the impedance of such an output buffer is performed using a circuit generally called a “calibration circuit”.
As disclosed in Japanese Patent Application Laid-open Nos. 2006-203405, 2005-159702, and 2007-110615, the calibration circuit includes a replica buffer having a configuration substantially identical to that of the output buffer. When a calibration operation is performed, in a state where an external resistor is connected to a calibration terminal, voltage that appears in the calibration terminal is compared with a reference voltage, thereby adjusting the impedance of the replica buffer. When an adjustment result of the replica buffer is then reflected in the output buffer, the impedance of the output buffer is set to a desired value.
In the calibration operation, adjusting steps including the voltage comparison and impedance update of the replica buffer are executed for a plurality of number of times. Thereby, the impedance of the replica buffer is brought close to the desired value. However, when the impedance adjustment is not correctly completed within a period during which a calibration operations are performed (a calibration period), the adjustment content is discarded assuming that some abnormality is generated. As a result, even when some abnormality is generated in the calibration operation, the impedance adjustment in a wrong direction is prevented.
A certain amount of time is necessary for the voltage comparison in the calibration operation, in the impedance change of the replica buffer, and so on. Thus, when a frequency of an external clock is high, it is not possible to execute the adjusting step in each clock cycle. In this case, the external clock is divided to generate an internal clock having a lower frequency, and in synchronism therewith, the adjusting step can be executed.
However, the calibration period (=tZQCS) is usually defined by the number of external clock cycles (64 clock cycles, for example). As a result, the larger a frequency-dividing number of the external clock cycles, the smaller the number of adjusting steps executable during the calibration period. That is, the number of times that the internal clock becomes active during one calibration period, i.e., the number of adjusting steps is m/n times, where m denotes the number of external clock cycles defining the calibration period and n denotes the frequency-dividing number. When the frequency of the external clock becomes higher, it inevitably becomes necessary to increase the frequency-dividing number n. This further decreases the number of adjusting steps executable during one calibration period.
Accordingly, when the frequency of the external clock becomes very high, there can be a case that the impedance adjustment is not completed during one calibration period. As described above, when such a case occurs, the adjustment result is conventionally discarded assuming that the abnormality is generated. However, when the number of adjusting steps executable during one calibration period becomes significantly small due to improvement of frequency, it is probable that the case that the impedance adjustment is not completed during one calibration period often occurs.
In such a case, when the adjustment content is discarded each time the impedance adjustment fails, it becomes impossible to reach a target impedance.